IPM6220ACAZ-T【PDF 12/15 页】IC REG 5OUT BUCK/LDO SYNC 24SSOP

12

Use a mix of input bypass capacitors to control the voltage

ripple across the MOSFETs. Use ceramic capacitors for the

high frequency decoupling and bulk capacitors to supply the

RMS current. Small ceramic capacitors can be placed very

close to the upper MOSFET to suppress the voltage induced

in the parasitic circuit impedances.

For board designs that allow through-hole components, the

Sanyo OS-CON?series offer low ESR and good

temperature performance.

For surface mount designs, solid tantalum capacitors can be

used, but caution must be exercised with regard to the

capacitor surge current rating. These capacitors must be

capable of handling the surge-current at power-up. The TPS

series available from AVX is surge current tested.

+12V Boost Converter Inductor Selection

The inductor value is chosen to provide the required output

power to the load.

where, Vinmin is the minimum input voltage, 4.9V; Dmax =

1/3, the maximum duty cycle; Ro is the minimum load

resistance; Vo is the nominal output voltage and F is the

switching frequency, 100kHz.

+12V Boost Converter Output Capacitor Selection

The total capacitance on the 12V output should be chosen

appropriately, so that the output voltage will be higher than

the undervoltage limit (9V) when the 5V Main soft-start time

has elapsed. This will avoid triggering of the 12V

undervoltage protection.

The maximum value of the boost capacitor, Comax that will

charge to 9V in the soft-start time, Tss, is shown below,

where L is the value of the boost inductor.

The output capacitor ESR and the boost inductor ripple

current determines the output voltage ripple. The ripple

voltage is given by:

and the maximum ripple current, I

L,

is given by:

where L is the boost inductor calculated above, 5V is the

boost input voltage and 3.3?is the maximum on time for the

boost MOSFET.

MOSFET Considerations

The logic level MOSFETs are chosen for optimum efficiency

given the potentially wide input voltage range and output

power requirements. Two N-channel MOSFETs are used in

each of the synchronous-rectified buck converters for the

PWM1 and PWM2 outputs. These MOSFETs should be

selected based upon r

DS(ON)

, gate supply requirements,

and thermal management considerations.

The power dissipation includes two loss components;

distributed between the upper and lower MOSFETs

according to duty cycle (see the following equations). The

conduction losses are the main component of power

dissipation for the lower MOSFETs. Only the upper MOSFET

has significant switching losses, since the lower device turns

on and off into near zero voltage.

The equations assume linear voltage-current transitions and

do not model power loss due to the reverse-recovery of the

lower MOSFETs body diode. The gate-charge losses are

dissipated by the IPM6220A and do not heat the MOSFETs.

However, a large gate-charge increases the switching time,

t

SW

, which increases the upper MOSFET switching losses.

Ensure that both MOSFETs are within their maximum

junction temperature at high ambient temperature by

calculating the temperature rise according to package

thermal-resistance specifications.

Layout Considerations

MOSFETs switch very fast and efficiently. The speed with

which the current transitions from one device to another

causes voltage spikes across the interconnecting impedances

and parasitic circuit elements. The voltage spikes can

degrade efficiency, radiate noise into the circuit, and lead to

device overvoltage stress. Careful component layout and

printed circuit design minimizes the voltage spikes in the

converter. Consider, as an example, the turn-off transition of

one of the upper PWM MOSFETs. Prior to turn-off, the upper

MOSFET is carrying the full load current. During the turn-off,

current stops flowing in the upper MOSFET and is picked up

by the lower MOSFET. Any inductance in the switched current

path generates a voltage spike during the switching interval.

Careful component selection, tight layout of the critical

components, and short, wide circuit traces minimize the

FIGURE 9. INPUT RMS CURRENT vs LOAD

1

2

3

4

5

3.3V AND 5V LOAD CURRENT

5

4.5

4

3.5

3

2.5

2

1.5

1

0.5

0

IN PHASE

OUT OF PHASE

3.3V

5V

Lmax

Vinmin

2

Dmax

2

?/DIV>

Ro

?/DIV>

2 Vo

2

?/DIV>

F

?/DIV>

----------------------------------------------------------------

=

Comax

Tss

L

--------- - 0.115礔

?/DIV>

=

V

RIPPLE

I

L

ESR

?/DIV>

=

I

L

5V

L

------ -

3.3

?/DIV>

=

P

UPPER

I

O

2

r

DS ON

( )

?/DIV>

V

OUT

?/DIV>

V

IN

----------------------------------------------------------- -

I

O

V

IN

?/DIV>

t

SW

?/DIV>

F

S

?/DIV>

2

----------------------------------------------------

+

=

P

LOWER

I

O

2

r

DS ON

( )

?/DIV>

V

IN

V

OUT

(

)

?/DIV>

V

IN

-------------------------------------------------------------------------------- -

=

IPM6220A

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